The present invention relates to a method of fabricating a semiconductor device containing a nonvolatile memory device and a logic device.
In fabrication of a semiconductor device containing both a nonvolatile memory device (PROM memory cells) and a logic device (CMOS transistors), a method in which improvement in reliability of the nonvolatile memory device and high performance of the logic device can be both realized is recently desired.
A conventional method of fabricating such a semiconductor device containing both of these devices will now be described with reference to drawings.
FIGS. 12(a) through 12(d), 13(a) through 13(d), 14(a) through 14(d), 15(a) through 15(d) and 16(a) through 16(c) are sectional views for showing procedures in the conventional method of fabricating a semiconductor device. In each of these drawings, Rmemo indicates a memory region where a nonvolatile memory device is to be formed, Rlogc indicates a logic region where a logic device (including P-channel and N-channel transistors) is to be formed, a reference numeral 101 denotes a silicon substrate of P-type monosilicon, a reference numeral 102 denotes an isolation insulating film of a silicon oxide film, a reference numeral 103 denotes a first implant protection film of a silicon oxide film, a reference numeral 105 denotes an N-type well, a reference numeral 107 denotes a p-type well, a reference numeral 108 denotes a gate insulating film of the nonvolatile memory device, a reference numeral 109 denotes a first polysilicon film, a reference numeral 110 denotes an ONO film (a laminated film including an oxide film, a nitride film and an oxide film), a reference numeral 114 denotes a gate insulating film of the logic device, a reference numeral 115 denotes a second polysilicon film, a reference numeral 117 denotes a control gate electrode of the nonvolatile memory device, a reference numeral 118 denotes an interelectrode insulating film of the nonvolatile memory device, a reference numeral 119 denotes a floating gate electrode of the nonvolatile memory device, a reference numeral 121 denotes a gate electrode of the logic device, a reference numeral 122 denotes a second implant protection film, a reference numeral 124 denotes a source/drain diffusion layer of the nonvolatile memory device, a reference numeral 126 denotes an LDD diffusion layer of the N-channel transistor, a reference numeral 128 denotes an LDD diffusion layer of the P-channel transistor, a reference numeral 129 denotes a sidewall spacer of the nonvolatile memory device and the logic device, a reference numeral 131 denotes a source/drain diffusion layer of the N-channel transistor, a reference numeral 133 denotes a source/drain diffusion layer of the P-channel transistor, and reference numerals 104, 106, 111, 112, 113, 116, 120, 123, 125, 127, 130 and 132 denote masks of photoresist films for use in ion implantation or etching.
First, in the procedure shown in FIG. 12(a), an isolation insulating film 102 of a silicon oxide film is formed in the memory region Rmemo and the logic region Rlogc on a silicon substrate 101, and a first implant protection film 103 of a silicon oxide film is then formed in a region surrounded with the isolation insulating film 102 on the silicon substrate 101.
Next, in the procedure shown in FIG. 12(b), an N-type well 105 is formed in the silicon substrate 101 by implanting ions of an N-type impurity (such as phosphorus) into a P-channel transistor formation region of the logic region Rlogc by using an N-type well formation mask 104 for covering the memory region Rmemo and an N-channel transistor formation region of the logic region Rlogc.
Then, in the procedure shown in FIG. 12(c), after removing the N-type well formation mask 104, a P-type well 107 is formed in the silicon substrate 101 by implanting ions of a P-type impurity (such as boron) into the entire memory region Rmemo and the N-channel transistor formation region of the logic region Rlogc by using a P-type well formation mask 106 for covering the P-channel transistor formation region of the logic region Rlogc. At the same time, impurity ions are implanted into the silicon substrate 101 by using the P-type well formation mask 106 for controlling the threshold values of the nonvolatile memory device and the N-channel transistor.
Next, in the procedure shown in FIG. 12(d), after removing the P-type well formation mask 106, the first implant protection film 103 in both the memory region Rmemo and the logic region Rlogc is removed by wet etching using buffered hydrofluoric acid.
Subsequently, in the procedure shown in FIG. 13(a), a gate insulating film 108 of a silicon oxide film of the nonvolatile memory device is formed in the memory region Rmemo and the logic region Rlogc by thermal oxidation, and a first polysilicon film 109 including phosphorus is then formed by CVD. The first polysilicon film 109 is to be formed into a floating gate electrode of the nonvolatile memory device. Thereafter, the first polysilicon film 109 is patterned by using a mask not shown so as to determine the dimension along the channel width of the nonvolatile memory device. Then, after removing the mask for patterning the first polysilicon film 109, an ON film 110a (a laminated film including an oxide film and a nitride film) to be formed into an interelectrode insulating film of the nonvolatile memory device is formed by the CVD.
Next, in the procedure shown in FIG. 13(b), the ON film 110a and the first polysilicon film 109 in the logic region Rlogc are successively removed by the dry etching using a mask 111 for covering the entire memory region Rmemo.
Then, in the procedure shown in FIG. 13(c), phosphorus ions (P+) are implanted for controlling the threshold value of the P-channel transistor in the logic region Rlogc by using a threshold controlling implantation mask 112 for covering the entire memory region Rmemo and the N-channel transistor formation region of the logic region Rlogc with the gate insulating film 108 remaining after the dry etching used as an implant protection film.
Next, in the procedure shown in FIG. 13(d), after removing the threshold control implantation mask 112, boron ions (B+) are implanted for controlling the threshold value of the N-channel transistor in the logic region Rlogc by using a threshold controlling implantation mask 113 for covering the memory region Rmemo and the P-channel transistor formation region of the logic region Rlogc with the gate insulating film 108 used as an implant protection film.
Then, in the procedure shown in FIG. 14(a), after removing the threshold controlling implantation mask 113, the gate insulating film 108 remaining in the logic region Rlogc is removed by the wet etching using buffered hydrofluoric acid.
Next, in the procedure shown in FIG. 14(b), a gate insulating film 114 of a silicon oxide film of the logic device is formed by the thermal oxidation. At this point, the surface of the ON film 110a in the memory region Rmemo is also oxidized into an ONO film 110. Then, a second polysilicon film 15 including phosphorus to be formed into a control gate electrode of the nonvolatile memory device and a gate electrode of the logic device is formed by the CVD.
Then, in the procedure shown in FIG. 14(c), the second polysilicon film 115, the first insulating film 110 and the first polysilicon film 109 in the memory region Rmemo are successively patterned by the dry etching using a stacked gate formation mask 116 for covering the entire logic region Rlogc and a gate formation region of the memory region Rmemo, so as to form a stacked gate of the nonvolatile memory device including a control gate electrode 117, an interelectrode insulating film 118 and a floating gate electrode 119.
Next, in the procedure shown in FIG. 14(d), after removing the stacked gate formation mask 116, the second polysilicon film 115 in the logic region Rlogc is patterned by the dry etching using a gate electrode formation mask 120 for covering the entire memory region Rmemo and a gate formation region of the logic region Rlogc, thereby forming a gate electrode 121 of the logic device.
Then, in the procedure shown in FIG. 15(a), after removing the gate electrode formation mask 120, the surfaces of the silicon layers (monosilicon and polysilicon layers) exposed on the silicon substrate 101 are oxidized by the thermal oxidation, thereby forming a second implant protection film 122 of a silicon oxide film covering the silicon substrate 101, the stacked gate of the nonvolatile memory device and the gate electrode 121 of the logic device. The second implant protection film 122 is also used as a protection film in ion implantation for forming a source/drain diffusion layer of the nonvolatile memory device.
Then, in the procedure shown in FIG. 15(b), a source/drain diffusion layer 124 of the nonvolatile memory device is formed by implanting, for example, arsenic ions (As+) and phosphorus ions (P+) by using a source/drain formation mask 123 for covering the entire logic region Rlogc.
Subsequently, in the procedure shown in FIG. 15(c), after removing the source/drain formation mask 123, the substrate is subjected to a heat treatment in an atmosphere of oxygen for recovering damage caused by the ion implantation. Thereafter, an LDD diffusion layer 126 of the N-channel transistor in the logic region Rlogc is formed by implanting phosphorus ions (P+) by using an LDD implantation mask 125 for covering the entire memory region Rmemo and the P-channel transistor formation region of the logic region Rlogc. This ion implantation is carried out in four steps at an ion acceleration voltage of approximately 50 keV, a dose of approximately 1xc3x971013 cmxe2x88x922 and an ion implantation angle inclined from the normal of the substrate by approximately 25 degrees. Furthermore, for suppressing punch-through, boron ions (B+) are implanted by using the LDD implantation mask 125 in four steps at an ion acceleration voltage of approximately 50 keV, a dose of approximately 3xc3x97102 cmxe2x88x922 and an ion implantation angle inclined by approximately 25 degrees.
Next, in the procedure shown in FIG. 15(d), after removing the LDD implantation mask 125, boron fluoride ions (BF2+) are implanted by using an LDD implantation mask 127 for covering the entire memory region Rmemo and the N-channel transistor formation region of the logic region Rlogc, thereby forming an LDD diffusion layer 128 of the P-channel transistor in the logic region Rlogc. This ion implantation is carried out in four steps at an ion acceleration voltage of approximately 50 keV, a dose of approximately 1xc3x971013 cmxe2x88x922 and an ion implantation angle inclined from the normal of the substrate by approximately 7 degrees.
Then, in the procedure shown in FIG. 16(a), after removing the LDD implantation mask 127, a TEOS film is deposited on the substrate, and formed into sidewall spacers 129 on the side faces of the stacked gate of the nonvolatile memory device and the gate electrode of the logic device by anisotropic dry etching.
Next, in the procedure shown in FIG. 16(b), arsenic ions or the like are implanted by using a source/drain implantation mask 130 for covering the entire memory region Rmemo and the P-channel transistor formation region of the logic region Rlogc, thereby forming a source/drain diffusion layer 131 of the N-channel transistor in the logic region Rlogc.
Then, in the procedure shown in FIG. 16(c), after removing the source/drain implantation mask 130, boron fluoride ions or the like are implanted by using a source/drain implantation mask 132 for covering the entire memory region Rmemo and the N-channel transistor formation region of the logic region Rlogc, thereby forming a source/drain diffusion layer 133 of the P-channel transistor in the logic region Rlogc.
As described above, with the floating gate electrode 119 of the nonvolatile memory device covered with the second implant protection film 122, the ion implantation for forming the source/drain diffusion layer 124 of the nonvolatile memory device is carried out. Therefore, the impurity ions such as arsenic and phosphorus are suppressed from punching through the floating gate electrode at the lower edge thereof to the gate insulating film below. Accordingly, the insulating property of the gate insulating film 108 of the nonvolatile memory device can be suppressed from degrading.
Furthermore, although the second implant protection film 122 cannot completely suppress the punch-through of the impurity ions, since the heat treatment is carried out in an atmosphere of oxygen after the impurity ion implantation, the gate insulating film 108 of the nonvolatile memory device, which is degraded in the insulating property by the damage caused in the impurity ion implantation, can be oxidized again so as to recover its insulating property. Accordingly, the nonvolatile memory device can be provided with a gate insulating film with high reliability.
The conventional method of fabricating a semiconductor device containing both a nonvolatile memory device and a logic device, however, has the following problems:
First, in the procedures shown in FIGS. 15(c) and 15(d), the second implant protection film 122 serving as the implant protection film for forming the source/drain diffusion layer of the nonvolatile memory device is formed so as to cover the entire substrate in the ion implantation for forming the LDD diffusion layer of the logic device. Therefore, the ion acceleration voltage inevitably has a large value (of approximately 50 keV). As a result, a shallow PN junction cannot be formed between the LDD diffusion layer and the P-type well, which makes it difficult to meet the demand for refinement of the device.
Secondly, in the procedure shown in FIG. 15(a), in the formation of the second implant protection film 122 serving as the implant protection film for forming the source/drain diffusion layer of the nonvolatile memory device by the thermal oxidation, oxygen enters both end portions of the gate insulating film 114 of the logic device to form an oxide film therein, which causes the so-called gate bird""s beak. As a result, variation in the channel length of the logic device is increased, so as to greatly vary the short channel effect and the transistor characteristic, namely, to lower the reliability.
Thirdly, in order to attain high performance (rapid operation) of a P-channel transistor, it is preferred to dope the gate electrode of an N-channel transistor with phosphorus and the gate electrode of the P-channel transistor with boron (namely, to employ a dual gate structure). In the procedure shown in FIG. 15(a), however, when the entire substrate is kept at a comparatively high temperature for the thermal oxidation, boron doped in the gate electrode of the P-channel transistor can be diffused into the semiconductor substrate, so as to cause variation in the threshold value. Accordingly, the gate electrodes of both the P-channel transistor and the N-channel transistor are inevitably doped with an N-type impurity as in the aforementioned conventional method, and it is thus very difficult to adopt the dual gate structure in the logic device.
An object of the invention is providing a method of fabricating a semiconductor device in which high reliability of a nonvolatile memory device and refinement of a logic device can be both realized.
Another object of the invention is providing a method of fabricating a semiconductor device in which a logic device can be easily formed in the dual gate structure.
The first method of this invention of fabricating a semiconductor device including, on a semiconductor substrate, a memory region where a nonvolatile memory device is disposed and a logic region where a logic device is disposed, comprises the steps of (a) forming, in the memory region, a first insulating film to be formed into a gate insulating film of the nonvolatile memory device, a first conducting film and a second insulating film and forming, in the logic region, a gate insulating film of the logic device; (b) forming a second conducting film on the semiconductor substrate after the step (a); (c) forming a stacked gate of the nonvolatile memory device including a control gate electrode, an interelectrode insulating film and a floating gate electrode of the nonvolatile memory device by patterning the second conducting film, the second insulating film and the first conducting film in the memory region with allowing the second conducting film to remain in the logic region; (d) forming, on the semiconductor substrate, a third insulating film for implant protection of the stacked gate after the step (c); (e) implanting impurity ions for forming source/drain diffusion layers of the nonvolatile memory device into regions on both sides of the floating gate electrode in the semiconductor substrate after the step (d); (f) removing at least a portion of the third insulating film disposed on the second conducting film by subjecting the third insulating film to anisotropic etching after the step (e); and (g) forming a gate electrode of the logic device by patterning the second conducting film remaining in the logic region.
According to this method, since the third insulating film for implant protection is not present in the logic region in forming a diffusion layer such as an LDD diffusion layer of the logic device after the step (g), the diffusion layer of the logic device can be provided with a shallow PN junction. Accordingly, the logic device can attain refinement. On the other hand, in forming the source/drain diffusion layer of the nonvolatile memory device, the side faces of the floating gate electrode of the nonvolatile memory device is covered with the third insulating film for implant protection. Therefore, it is possible to suppress the degradation in the insulating property of the gate insulating film derived from the impurity punching through the lower edge of the floating gate electrode to the gate insulating film of the nonvolatile memory device. As a result, not only the performance of the nonvolatile memory can be retained but also the logic device can be refined.
When the method further comprises, between the step (e) and the step (f), a step of subjecting the semiconductor substrate to a heat treatment in an oxidizing atmosphere, damage of the end portions of the gate insulating film of the nonvolatile memory device derived from the impurity ion implantation can be recovered, so that the nonvolatile memory device can attain higher performance.
When the method further comprises the steps of implanting impurity ions for forming an LDD diffusion layer of the logic device by using the gate electrode as a mask after the step (g); forming sidewall spacers on side faces of the floating gate electrode, the interelectrode insulating film and the control gate electrode of the nonvolatile memory device and side faces of the gate electrode of the logic device after forming the LDD diffusion layer of the logic device; and implanting impurity ions for forming source/drain diffusion layers of the logic device into the logic region by using the gate electrode and the sidewall spacers used as a mask, the logic device of the semiconductor device can be formed in an LDD structure suitable to refinement.
The second method of this invention of fabricating a semiconductor device including, on a semiconductor substrate, a memory region where a nonvolatile memory device is disposed and a logic region where a logic device is disposed, comprises the steps of (a) forming, in the memory region, a first insulating film to be formed into a gate insulating film of the nonvolatile memory device, a conducting film and a second insulating film and forming, in the logic region, a gate insulating film of the logic device; (b) forming a polysilicon film on the semiconductor substrate after the step (a); (c) implanting N-type impurity ions into portions of the polysilicon film disposed in the memory region and an N-channel logic element formation region of the logic region; (d) forming a stacked gate of the nonvolatile memory device including a control gate electrode, an interelectrode insulating film and a floating gate electrode by patterning the polysilicon film, the second insulating film and the conducting film in the memory region with allowing the polysilicon film to remain in the logic region; (e) forming, on the semiconductor substrate, a third insulating film for implant protection of the stacked gate after the step (d); (f) implanting impurity ions for forming source/drain diffusion layer of the nonvolatile memory device into regions on both sides of the floating gate electrode in the semiconductor substrate after the step (e); (g) removing at least a portion of the third insulating film disposed on the polysilicon film by subjecting the third insulating film to anisotropic etching after the step (f); (h) implanting P-type impurity ions into a portion of the polysilicon film disposed in a P-channel logic element formation region of the logic region after the step (f) or before or after the step (g); and (i) forming a gate electrode of the logic device by patterning the polysilicon film remaining in the logic region.
According to this method, in addition to the effects attained by the first method of fabricating a semiconductor device, the logic device can be formed from a transistor having a higher operation speed owing to the dual gate structure.
When the method further comprises, after the step (f) or before the step (h), a step of subjecting the semiconductor substrate to a heat treatment in an oxidizing atmosphere, damage of the end portions of the gate insulating film of the nonvolatile memory device derived from the impurity ion implantation can be recovered, so that the nonvolatile memory device can attain higher performance.
When the method further comprises the steps of implanting impurity ions for individually forming LDD diffusion layers of a P-channel logic element and an N-channel logic element of the logic device by using the gate electrode as a mask after the step (i); forming sidewall spacers on side faces of the floating gate electrode, the interelectrode insulating film and the control gate electrode of the nonvolatile memory device and side faces of the gate electrode of the logic device after forming the LDD diffusion layers; and implanting impurity ions for individually forming source/drain diffusion layers of the P-channel logic element and the N-channel logic element in the logic region by using the gate electrode and the sidewall spacers as a mask, the logic device of the semiconductor device can be formed in an LDD structure suitable to refinement.
In any of the first and second methods of fabricating a semiconductor device, the third insulating film for implant protection is preferably a silicon oxide film formed by CVD.